Non-volatile memories are an important component of numerous electronic devices. Electrically erasable programmable read-only memory (“EEPROM”) is a particularly useful non-volatile memory. Flash memory, a type of EEPROM memory, allows multiple memory locations to be written to or erased in one operation.
In flash memory, information is stored in an array of floating gate transistors (usually floating gate MOSFET transistors), or cells. A floating gate MOSFET may be programmed by Fowler-Nordheim tunneling or by channel hot electron injection at the drain region.
In some memory arrays, memory cells on unselected bitlines may be affected during write operations on selected bitlines. In FIG. 1, a portion of an exemplary memory array 10 contains four bitlines—BL0 14, BL1 16, BL2 18, and BL3 20. (The following description of a configuration of a memory array is for exemplary purposes only and it will be apparent to those of skill in the art that the conditions associated with this particular configuration may be found in other configurations of memory arrays.) Each bitline is coupled to a memory cell 80, 78, 82, 84. Each memory cell, for instance memory cell 78, comprises a double gate NMOS transistor 54, with a floating gate 72 and a control gate 74. The memory cell 78 also has an NMOS select transistor 66 with a control gate 76 coupled to a word line 50 and a drain terminal coupled to bitline 16. The source terminal of the double gate NMOS transistor 54 is coupled to an array VSS line AVSS 52, which has a potential VAVSS. The control gate 74 of the double gate NMOS transistor 54 is coupled to a select line 56. BL1 16 also has a capacitor Pbulk 48.
High voltage programming even bitlines (“HV_PROG_E”) line 60 and high voltage programming odd bitlines (“HV_PROG_O”) line 62 enable programming on even and odd bitlines, respectively. For instance, when a low voltage is asserted on HV_PROG_E 60, PMOS transistors 26 and 30 on BL0 14 and BL2 18, respectively, conduct current from voltage source 12, raising the potential on bitlines BL0 14 and BL2 18 to a potential corresponding to a high voltage programming voltage Vmm from a voltage source 12 applied at the source terminal of the PMOS transistors 26, 30. The odd bitlines, BL1 16 and BL3 20 are not raised to the potential Vmm due to PMOS transistors 28 and 32, which do not conduct unless low voltage is asserted on HV_PROG_O 62. In this example, there is one latch 22 per two bitlines BL0 14, BL1 16 (also latch 24 for bitlines BL2 18 and BL3 20) which determine the data to be written to the memory cell on the selected bitline via voltage Q applied to the gates transistors 42 and 40 (or 38 and 36, when latch 24 is employed) on the bitlines.
If a write operation is performed on the even bitlines, BL0 14 and BL2 18, and the odd bitlines BL1 16 and BL3 20, are not selected and are floating, parasitic, or capacitive, coupling between the selected bitlines and the unselected bitlines may affect the memory cells on the unselected bitlines. For instance, if even bitlines BL0 14 and BL2 18 are driven to a high voltage of around 12 V, capacitive coupling 44, 46 between selected bitlines BL0 14 and BL2 18 and unselected bitline BL1 can also drive the floating, unselected bitline BL1 to a high voltage because the capacitor 48 on BL1 will start to charge as a result of charge redistribution. The memory cell 78 on the unselected bitline BL1 can be affected by this charge distribution. If the threshold of the memory cell 78 is about 7 V, any charge distribution in excess of 7 V on the unselected bitline 16 will cause Fowler-Nordheim tunneling at the floating gate 72 of the memory cell 78. If the memory cell 78 is strongly erased, the tunneling can cause the memory cell 78 to become weakly erased by degrading the negative charge on the floating gate 72. Over time, this may cause permanent damage to the memory cell, i.e., the cell may be “flipped.”
Therefore, there is a need for a means to prevent parasitic coupling between selected bitlines and unselected bitlines during write operations in a memory array. It would also be desirable to prevent unselected bitlines from floating during a write operation on selected bitlines.